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Description: ATMEGA16检测按键的程序，去抖动延时-ATMEGA16 detection key procedures, de-jitter delay
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Size: 54272 |
Author: regerg |
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Description: 上一节讲了多任务中蜂鸣器驱动程序的框架，这节继续利用多任务处理的方式，在主函数中利用累计主循环次数来实现独立按键的检测。要教会大家四个知识点：
第一点：独立按键的驱动程序框架
第二点：用累计主循环次数来实现去抖动的延时。
第三点：灵活运用防止按键不松手后一直触发的按键自锁标志。
第四点：在按键去抖动延时计时中，添加一个抗干扰的软件监控判断。一旦发现瞬间杂波干扰，马上把延时计数器清零。
这种方法是我在复杂的工控项目中总结出来的。以后凡是用到开关感应器的地方，都可以用类似的方法实现软件上的抗干扰处理。
具体内容，请看源代码讲解。
（1）用矩阵键盘中的S1和S5号键作为独立按键，记得把输出线P0.4一直输出低电平，模拟独立按键的触发地GND。
（2）实现功能：有两个独立按键，每按一个独立按键，蜂鸣器发出“滴”的一声后就停。-Previous section talked about the framework of multi-tasking in buzzer driver, this section continue to use the way multi-task processing, are used to detect the use of separate keys cumulative primary cycles in the main function. Knowledge to teach you four points:
First point: independent key driver framework
The second point: The cumulative number of cycles to achieve the main debounce delay.
The third point: flexible use grimdeath prevent the keys from the lock button has been triggered flag.
The fourth point: the key to timing jitter delay, add an anti-jamming software monitoring judgments. Once an instant clutter found immediately to the delay counter is cleared.
This approach is summed up in my complex industrial projects. After all switch sensors used in place anti-jamming processing software can be achieved on a similar approach.
Details, see the source code to explain.
(1) with S1 and S5 matrix keypad number keys as a separate button, remember to out
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Size: 3072 |
Author: 高飞 |
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Description: 上一节讲了多任务中蜂鸣器驱动程序的框架，这节继续利用多任务处理的方式，在主函数中利用累计主循环次数来实现独立按键的检测。要教会大家四个知识点：
第一点：独立按键的驱动程序框架
第二点：用累计主循环次数来实现去抖动的延时。
第三点：灵活运用防止按键不松手后一直触发的按键自锁标志。
第四点：在按键去抖动延时计时中，添加一个抗干扰的软件监控判断。一旦发现瞬间杂波干扰，马上把延时计数器清零。
这种方法是我在复杂的工控项目中总结出来的。以后凡是用到开关感应器的地方，都可以用类似的方法实现软件上的抗干扰处理。
具体内容，请看源代码讲解。
记得把输出线P0.4一直输出低电平，模拟独立按键的触发地GND。
实现功能：有两个独立按键，每按一个独立按键，蜂鸣器发出“滴”的一声后就停。-Previous section talked about the framework of multi-tasking in buzzer driver, this section continue to use the way multi-task processing, are used to detect the use of separate keys cumulative primary cycles in the main function. Knowledge to teach you four points:
First point: independent key driver framework
The second point: The cumulative number of cycles to achieve the main debounce delay.
The third point: flexible use grimdeath prevent the keys from the lock button has been triggered flag.
The fourth point: the key to timing jitter delay, add an anti-jamming software monitoring judgments. Once an instant clutter found immediately to the delay counter is cleared.
This approach is summed up in my complex industrial projects. After all switch sensors used in place anti-jamming processing software can be achieved on a similar approach.
Details, see the source code to explain.
I remember the output lines P0.4 output has been low, the analog trigger buttons i
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Size: 3072 |
Author: 高飞 |
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Description: EMDA is based on a per-node reservation
of a block of contiguous transmission opportunities that are
properly dimensioned. Moreover, we further improve the neardeterministic
access of EMDA by using short jamming periods
just before these reservations. Extensive simulation results show
that our proposed MAC enlarges the voice capacity and uniformly
distribute it over the WMN. It also provide a better
performance in guaranteeing hard delay constraints, lower jitter
and lower packet losses compared to other MAC
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Size: 441344 |
Author: annariel |
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Description: 基于ACE的http服务器--JAWS，JAWS具有高吞吐量和可伸缩性、低时延和抖动，这表明面向模式和面向框架的软件架构是高效率的。
JAWS框架本身是使用ACE框架开发的，为本书中的大多数模式提供了面向对象的实现。-ACE HTTP server based on--JAWS, JAWS has the advantages of high throughput and scalability, low delay and jitter, which indicates that the pattern oriented and object-oriented framework of software architecture is efficient.
JAWS framework itself is to use the ACE framework for the development, provides the implementation of object oriented model for most in this book.
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Size: 374784 |
Author: 张伟烽 |
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Description: 本代码利用Verilog实现了键位按下时的抖动毛刺的滤波处理，主要包含电平检查模块和一个延迟模块。-This code implements the use of Verilog jitter filtering glitches keys pressed, the main level include checking module and a delay module.
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Size: 44032 |
Author: chengzetao |
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Description: STM32f103ZET6，通过定时中断实现按键去抖动，是延时方法去抖动的改进。程序中通过定时去抖动，控制LED翻转，是基本模型。在触摸屏按键按键等程序中都可以以此为函数模块。-STM32f103ZET6, realized by the timer interrupt button to jitter, jitter is the delay ways to improve. Program by timing de-jitter, flip control LED, is the basic model. Buttons and other buttons on the touch screen can be programmed as a function of the module.
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Size: 2048 |
Author: xiaohu |
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Description: The new emerging QoS architectures are motivated by the desire to improve the
overall performance of an IP network. Differentiated Services (Diffserv) define a model for
implementing scalable differentiation of QoS in the Internet. Multiprotocol Label
Switching (MPLS) is a fast label-based switching technique that offers new QoS
capabilities for large scale IP networks. When an MPLS network supports DiffServ, traffic
flows can receive class-based network treatment that provides bases for QoS guarantees.
The objective of this work is to study the influence of the QoS mechanism via
DiffServ-MPLS on network parameters such as jitter, delay and throughput. The
comprehensive study showed general improvement in the throughput, jitter and delay
particularly of voice and video transmission when using DiffServ-aware MPLS network as
compared to pure IP only or MPLS only.
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Size: 444416 |
Author: muhand |
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Description: 按键驱动程序（混杂设备模型）
软件去抖动的原理就是：
定时器延时时刻到的时刻，按键的状态
要和在 定时器 启动 时刻按键的状态一致。-Key driver (hybrid device model)
Jitter is the principle of the software to:
State timer delay time to time, the keys
To start the timer and the key moments in a consistent state.
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Size: 2048 |
Author: liliang |
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Description: 单个按键扫描程序
1、程序说明：
该例程演示了接在单片机P1端口上的五个按键。
通过程序扫描对应按键端口的电平状态来确定是否该键按下，
通过机械按键按下和松开时有抖动现象，需在程序中适当延时消除抖动，
避免识别到错误信息，该程序同时具有等待按键释放的功能。
2、实验操作
将拨码开关S10的SMG端拨到ON端，表示该端接通。
同时把该拨码开关的其他端置为断开状态，即不拨到ON端。
否则将影响到实验效果。将程序下载到开发板中运行后，
依次按下S2到S6任意一个键，将在数码管上显示相应的键值-Single key scanner
1, program instructions:
This routine demonstrates the five buttons connected to the P1 port on the microcontroller.
Determines whether the key is pressed by the program scan corresponding to the level state of the key port,
By mechanical press and release the button when the jitter phenomenon, the need for appropriate delay in the process of eliminating jitter,
Avoid identifying the error message, and the program has the function of waiting for the release of the key.
2, experimental operation
The dial switch SMG S10 end of the ON to the side, indicating that the end is connected.
At the same time, the other end of the dial switch is in a disconnected state, that is, the switch is not transferred to the ON terminal.
Otherwise, it will affect the experimental results. After the program is downloaded to the development board to run,
In order to press S2 to S6 any key, the corresponding key will display in the digital tube
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Size: 38912 |
Author: yushizhen |
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Description: 利用AWK程序分析跟踪文件，对吞吐量、延迟丢包率、延时变化量、端对端的延迟时间进行分析。-The AWK program is used to analyze the trace file, and the throughput, delay packet loss rate, jitter and measure-delay are analyzed.
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Size: 3072 |
Author: 李玉杰 |
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Description: 51单片机新型按键扫描，不用10ms延时消抖，实时性大大提高。每个按键有长按短按功能，采用结构体对象化编程，增加按键极度方便。(The new key scan does not use 10ms delay to eliminate jitter, and the real-time performance is greatly improved. Each button has a long press, a short press function, the use of structured object programming, increasing the key, extremely convenient.)
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Size: 3072 |
Author: 沧海一瞬
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Description: PLL，即锁相环。是FPGA中的重要资源。由于一个复杂的FPGA系统往往需要多个不同频率，相位的时钟信号。所以，一个FPGA芯片中PLL的数量是衡量FPGA芯片能力的重要指标。FPGA的设计中，时钟系统的FPGA高速的设计极其重要，一个低抖动, 低延迟的系统时钟会增加FPGA设计的成功率。本例程调用Xilinx提供的PLL核来产生不同频率的时钟, 并把其中的一个时钟输出到FPGA外部IO上, 也就是开发板的SMA接口上。(PLL, pll. It's an important resource in FPGA. Because a complex FPGA system often requires multiple clock signals with different frequencies and phases. Therefore, the number of PLL in a FPGA chip is an important indicator of the ability of FPGA chip. In the design of FPGA, the high speed design of clock system FPGA is extremely important. A low jitter and low delay system clock will increase the success rate of FPGA design. This routine calls the PLL core provided by Xilinx to generate clocks of different frequencies, and outputs one of the clocks to the external IO of the FPGA, that is, the SMA interface of the development board.)
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Size: 221184 |
Author: cddwishper
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Description: wsn parameters like jitter, packet delevary ratio, end to end delay etc...
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Size: 2048 |
Author: miriyala
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